The background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
Real-Time Operating System (“RTOS”) kernels used in embedded systems typically use event flags, represented by bits that are grouped together in clusters called event groups. Such event groups are frequently tested using AND and OR computations by the RTOS kernel against a bit mask. While simple AND and OR computations can be sequentially combined to perform more powerful operations, such as multiplication, division, and variable testing, it is advantageous to use more complicated base comparisons than simple AND and OR computations.
U.S. Pat. No. 5,781,789 to Narayan teaches a mask decoder circuit that receives an input bit mask that is representative of several masks, and produces submasks in parallel by selectively outputting portions of the input bit mask to an output bit mask. The mask decoder circuit is tied to a clock cycle such that as the input clock cycle increases, the output bit mask changes using a multiplexor selector. Narayan's mask decoder circuit, however, requires the multiplexor to select submasks as a function of a clock cycle. Locking a mask decoder circuit to a clock cycle may provide a method of regularly filtering through an input mask, but is rather limited.
U.S. Pat. No. 7,254,699 to Shepherd teaches a microprocessor/microcontroller architecture that re-aligns misaligned data by copying two portions of unaligned data into a first storage location and a second storage location, rotating the data in the two storage locations until the data is properly aligned, and then combines the two aligned portions of data (usually using an OR computation) into a result storage location. This allows the microprocessor/microcontroller to transmit large chunks of data with less bits by using compression algorithms that frequently misalign the data and decompression algorithms that realign data.
U.S. Pat. No. 7,475,301 to Adkisson teaches an increment/decrement circuit that receives and aligns debug data in time with a constantly incrementing counter. Such a circuit is able to perform accumulation operations between two portions of a multi-bit block. However Adkisson's circuit fails to allow a user to embed operations within the multi-bit block itself.
Thus, there remains a need for a system and method that allows a ROTS to perform more than simple AND and OR operations using a single multi-bit block.